Definition of Set-up, Hold and Propagation in Flip-Flops

Figure 1 shows a basic diagram of a D Flip-Flop. Flip-Flops are very common elements in synchronous designs where clock signal provides the timing to various elements and clock domains.

   Figure 1: D Flip-Flop

Setup time and hold time describe the timing requirements for the D input of a Flip-Flop with respect to the Clk input. Setup and hold time define a window of time which the D input must be valid and stable in order to assure valid data on the Q output.

Setup Time (Tsu) – Setup time is the time that the D input must be valid before the Flip-Flop samples.

Hold Time (Th) – Hold time is the time that D input must be maintained valid after the Flip-Flop              samples.

Propagation Delay (Tpd) – Propagation delay is the time that takes to the sampled D input to propagate to the Q output.

 Figure 2: D-Flip Flop Timing Diagram

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