Maximum Operating Frequency of a Flip-Flop

The maximum operating frequency of a single flip-flop cannot be calculated without its surrounding components. Its position in a clock tree or in a synchronous counter can bring the maximum frequency down to 1Hz or with a good timing design can be high as the maximum frequency of this specific flip-flop.

This Q&A proposes two questions regarding this topic.

The question is applicable for both FPGA and VLSI development,

Figure 1: D Flip Flop

Question A

 For a flip-flop which connected in a toggle configuration:

Tsu = 2ns

Th   = 1ns

Tcq(max) = 2ns

What will be the maximum operating frequency of this flip-flop? (Tcq=clock-to-q)

Figure 2: T Flip Flop

Question B

 For two-cascaded flip-flops sharing the same clock.  The Data pin of the second flip-flop is output from a combinatorial logic of output of flip-flop1 and other signals.

Flip-flops:

Tsu = 2ns

Th   = 1ns

Tcq(max)  = 2ns

Logic:

                        Tpd = 6ns

What will be the maximum operating frequency of the design?

Figure 3: Flip-Flop with Combinatorial Logic

Answer A 

Tsu = 2ns

 Th   = 1ns

Tcq(max)  = 2ns

Figure 4: T Flip-Flop Timing Diagram

The maximum operating frequency will be 1/(Tsu+Tcq(max)).

The Th is smaller then the Tcq therefore is not calculated.

Answer B 

Tsu = 2ns

 Th   = 1ns

Tcq(max)  = 2ns

                        Tpd = 6ns

If you cascade two flip-flops with some logic in between then

Fmax = 1/[Tcq(first_FF) + Tpdlogic+ Tsu (second_FF)]

Please note:  Th < Tcq(min) + Tpdlogic(min)

Home | Interview Quiz | Board Design | System Design | Lab Stuff | About